Extended display identification data (EDID) is a data structure provided by a digital display to describe its capabilities to a video source (e.g. graphics card or set-top box). It is what enables a modern personal computer to know what kinds of monitors are connected to it. EDID is defined by a standard published by the Video Electronics Standards Association (VESA). The EDID includes manufacturer name and serial number, product type, phosphor or filter type, timings supported by the display, display size, luminance data and (for digital displays only) pixel mapping data.
EDID structure versions range from v1.0 to v1.4; all these define upwards-compatible 128-byte structures. EDID structure v2.0 defined a new 256-byte structure, but subsequently has been deprecated and replaced by v1.3. HDMI 1.0 – 1.3c uses EDID structure v1.3.
DisplayID is a standard targeted to replace EDID and E-EDID extensions with a uniform format suited for both PC monitor and consumer electronics devices.
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The channel for transmitting the EDID from the display to the graphics card is usually the I²C bus, defined in DDC2B (DDC1 used a different serial format which never gained popularity).
Before DDC and EDID were defined, there was no standard way for a graphics card to know to what kind of display device it was connected. Some VGA connectors in personal computers provided a basic form of identification by connecting one, two or three pins to ground, but this coding was not standardized.
The EDID is often stored in the monitor in a memory device called a serial PROM (programmable read-only memory) or EEPROM (electrically erasable PROM) and is accessible via the I²C bus at address 0x50.[1] The EDID PROM can often be read by the host PC even if the display itself is turned off.
Many software packages can read and display the EDID information, such as read-edid[2] and PowerStrip[3] for Microsoft Windows and XFree86 (which will output the EDID to the log if verbose logging is on (startx -- -logverbose 6)) for Linux and BSD unix. Mac OS X natively reads EDID information (see /var/log/system.log or hold down Cmd-V on startup) and programs such as SwitchResX[4] or DisplayConfigX[5] can display the information as well as use it to define custom resolutions.
Enhanced EDID was introduced at the same time as E-DDC; it introduced EDID structure version 1.3 which supports multiple extensions blocks and deprecated EDID version 2.0 structure (although it can be supported as an extension). Data fields for preferred timing, range limits, monitor name are required in E-EDID. E-EDID also supports dual GTF timings and aspect ratio change.
With the use of extensions, E-EDID string can be lengthened up to 32 KBytes.
Some graphics card drivers have historically coped poorly with the EDID, using only its standard timing descriptors rather than its Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were read, the drivers are/were still often limited by the standard timing descriptor limitation that the horizontal/vertical resolutions must be evenly divisible by 8. This means that many graphics cards cannot express the native resolutions of the most common wide screen flat panel displays and liquid crystal display televisions. The number of vertical pixels is calculated from the horizontal resolution and the selected aspect ratio. To be fully expressible, the size of wide screen display must thus be a multiple of 16×9 pixels. For 1366×768 pixel Wide XGA panels the nearest resolution expressible in the EDID standard timing descriptor syntax is 1360×765 pixels, typically leading to 3 pixel thin black bars. Specifying 1368 pixels as the screen width would yield an unnatural screen height of 769.5 pixels.
Many Wide XGA panels do not advertise their native resolution in the standard timing descriptors, instead offering only a resolution of 1280×768. Some panels advertise a resolution only slightly smaller than the native, such as 1360×765. For these panels to be able to show a pixel perfect image, the EDID data must be ignored by the display driver or the driver must correctly interpret the DTD and be able to resolve resolutions whose size is not divisible by 8. Special programs are available to override the standard timing descriptors from EDID data; PowerStrip for Microsoft Windows and SwitchResX for Mac OS X. Even this is not always possible however, as some vendors' graphics drivers (notably those of Intel) require specific registry hacks to implement custom resolutions, which can make it very difficult to use the screen's native resolution.[6]
| Bytes | Description | |
|---|---|---|
| 0–19 | Header information | |
| 0–7 | Fixed header pattern: 00 FF FF FF FF FF FF 00 |
|
| 8–9 | Manufacturer EISA ID. Encoded as 3 5-bit letters (1=A, 26=Z), big-endian, with msbit reserved. | |
| Bit 15 | (Reserved, always 0) | |
| Bits 14–10 | First letter of manufacturer ID (byte 8, bits 6–2) | |
| Bits 9–5 | Second letter of manufacturer ID (byte 8, bit 1 through byte 9 bit 5) | |
| Bits 4–0 | Third letter of manufacturer ID (byte 9 bits 4–0) | |
| 10–11 | Manufacturer product code. 16-bit number, little-endian. | |
| 12–15 | Serial number. 32 bits, little endian. | |
| 16 | Week of manufacture. Week numbering is not consistent between manufacturers. | |
| 17 | Year of manufacture, less 1990. (1990–2245). If week=255, it is the model year instead. | |
| 18 | EDID version, usually 1 (for 1.3) | |
| 19 | EDID revision, usually 3 (for 1.3) | |
| 20–24 | Basic display parameters. | |
| 20 | Video input parameters bitmap | |
| Bit 7=1 | Digital input. If set, the following bit definitions apply: | |
| Bits 6–1 | Reserved, must be 0 | |
| Bit 0 | Signal is compatible with VESA DFP 1.x TMDS CRGB, 1 pixel per clock, up to 8 bits per color, MSB aligned, | |
| Bit 7=0 | Analog input. If clear, the following bit definitions apply: | |
| Bits 6–5 | Video white and sync levels, relative to blank: 00=+0.7/−0.3 V; 01=+0.714/−0.286 V; 10=+1.0/−0.4 V; 11=+0.7/0 V | |
| Bit 4 | Blank-to-black setup (pedestal) expected | |
| Bit 3 | Separate sync supported | |
| Bit 2 | Composite sync (on HSync) supported | |
| Bit 1 | Sync on green supported | |
| Bit 0 | VSync pulse must be serrated when somposite or sync-on-green is used. | |
| 21 | Maximum horizontal image size, in centimetres (max 292 cm/115 in at 16:9 aspect ratio) | |
| 22 | Maximum vertical image size, in centimetres. If either byte is 0, undefined (e.g. projector) | |
| 23 | Display gamma, minus 1, times 100 (range 1.00–3.54) | |
| 24 | Supported features bitmap | |
| Bit 7 | DPMS standby supported | |
| Bit 6 | DPMS suspend supported | |
| Bit 5 | DPMS active-off supported | |
| Bits 4–3 | Display type: 00=monochrome; 01=RGB colour; 10=non-RGB multicolour; 11=undefined | |
| Bit 2 | Standard sRGB colour space. Bytes 25–34 must contain sRGB standard values. | |
| Bit 1 | Preferred timing mode specified in descriptor block 1. | |
| Bit 0 | GTF supported with default parameter values. | |
| 25–34 | Chromaticity coordinates. 10-bit CIE xy coordinates for red, green, blue, and white. [0–1023/1024]. |
|
| 25 | Red and green least-significant bits | |
| Bits 7–6 | Red x value least-significant 2 bits | |
| Bits 5–4 | Red y value least-significant 2 bits | |
| Bits 3–2 | Green x value least-significant 2 bits | |
| Bits 1–0 | Green y value least-significant 2 bits | |
| 26 | Blue and white least-significant 2 bits | |
| 27 | Red x value most significant 8 bits. 0–255 encodes 0–0.996 (255/256); 0–0.999 (1023/1024) with lsbits | |
| 28 | Red y value most significant 8 bits | |
| 29–30 | Green x and y value most significant 8 bits | |
| 31–32 | Blue x and y value most significant 8 bits | |
| 33–34 | Default white point x and y value most significant 8 bits | |
| 35–37 | Established timing bitmap. Supported bitmap for very common timing modes. | |
| 35 | Bit 7 | 720×400 @ 70 Hz |
| Bit 6 | 720×400 @ 88 Hz | |
| Bit 5 | 640×480 @ 60 Hz | |
| Bit 4 | 640×480 @ 67 Hz | |
| Bit 3 | 640×480 @ 72 Hz | |
| Bit 2 | 640×480 @ 75 Hz | |
| Bit 1 | 800×600 @ 56 Hz | |
| Bit 0 | 800×600 @ 60 Hz | |
| 36 | Bit 7 | 800×600 @ 72 Hz |
| Bit 6 | 800×600 @ 75 Hz | |
| Bit 5 | 832×624 @ 75 Hz | |
| Bit 4 | 1024×768 @ 87 Hz, interlaced (1024×768i) | |
| Bit 3 | 1024×768 @ 60 Hz | |
| Bit 2 | 1024×768 @ 72 Hz | |
| Bit 1 | 1024×768 @ 75 Hz | |
| Bit 0 | 1280×1024 @ 75 Hz | |
| 37 | Bit 7 | 1152x870 @ 75 Hz (Apple Macintosh II) |
| Bits 6–0 | Other manufacturer-specific display modes | |
| 38–53 | Standard timing information. Up to 8 2-byte fields describing standard display modes. Unused fields are filled with 01 01 |
|
| Byte 0 | X resolution, less 31, divided by 8 (256–2288 pixels) | |
| Byte 1 bits 7–6 | X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9. (Versions prior to 1.3 defined 00 as 1:1.) |
|
| Byte 1 bits 5–0 | Vertical frequency, less 60 (60–123 Hz) | |
| 54–71 | Descriptor 1 | Descriptor blocks. Detailed timing descriptors, in decreasing preference order. After all detailed timing descriptors, additional descriptors are permitted:
|
| 72–89 | Descriptor 2 | |
| 90–107 | Descriptor 3 | |
| 108–125 | Descriptor 4 | |
| 126 | Number of extensions to follow. 0 if no extensions. | |
| 127 | Checksum. Sum of all 128 bytes should equal 0 (mod 256). | |
| Bytes | Description | |
|---|---|---|
| 0–1 | Pixel clock in 10 kHz units. (0.01–655.35 MHz, little-endian) | |
| 2 | Horizontal active pixels 8 lsbits (0–4095) | |
| 3 | Horizontal blanking pixels 8 lsbits (0–4095) End of active to start of next active. | |
| 4 | Bits 7–4 | Horizontal active pixels 4 msbits |
| Bits 3–0 | Horizontal blanking pixels 4 msbits | |
| 5 | Vertical active lines 8 lsbits (0–4095) | |
| 6 | Vertical blanking lines 8 lsbits (0–4095) | |
| 7 | Bits 7–4 | Vertical active lines 4 msbits |
| Bits 3–0 | Vertical blanking lines 4 msbits | |
| 8 | Horizontal sync offset pixels 8 lsbits (0–1023) From blanking start | |
| 9 | Horizontal sync pulse width pixels 8 lsbits (0–1023) | |
| 10 | Bits 7–4 | Vertical sync offset lines 4 lsbits (0–63) |
| Bits 3–0 | Vertical sync pulse width lines 4 lsbits (0–63) | |
| 11 | Bits 7–6 | Horizontal sync offset pixels 2 msbits |
| Bits 5–4 | Horizontal sync pulse width pixels 2 msbits | |
| Bits 3–2 | Vertical sync offset lines 2 msbits | |
| Bits 1–0 | Vertical sync pulse width lines 2 msbits | |
| 12 | Horizontal display size, mm, 8 lsbits (0–4095 mm, 161 in) | |
| 13 | Vertical display size, mm, 8 lsbits (0–4095 mm, 161 in) | |
| 14 | Bits 7–4 | Horizontal display size, mm, 4 msbits |
| Bits 3–0 | Vertical display size, mm, 4 msbits | |
| 15 | Horizontal border pixels (each side; total is twice this) | |
| 16 | Vertical border lines (each side; total is twice this) | |
| 17 | Features bitmap | |
| Bit 7 | Interlaced | |
| Bits 6–5 | Stereo mode: 00=No stereo; other values depend on bit 0: Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar, sync=1 during left; 11=4-way interleaved stereo Bit 0=1 2-way interleaved stereo: 01=Right image on even lines; 10=Left image on even lines; 11=side-by-side |
|
| Bits 4–3 | Sync type: 00=Analog composite; 01=Bipolar analog composite; 10=Digital composite (on HSync); 11=Digital separate | |
| Bit 2 | If digital separate: Vertical sync polarity (1=positive) Other types: VSync serrated (HSync during VSync) |
|
| Bit 1 | If analog sync: Sync on all 3 RGB lines (else green only) Digital: HSync polarity (1=positive) |
|
| Bit 0 | 2-way line-interleaved stereo, if bits 4–3 are not 00. | |
When used for another descriptor, the pixel clock and some other bytes are set to 0:
| Bytes | Description |
|---|---|
| 0–1 | Zero, indicates not a detailed timing descriptor |
| 2 | Zero |
| 3 | Descritptor type. FA–FF currently defined. 00–0F reserved for vendors. |
| 4 | Zero |
| 5–17 | Defined by descriptor type. If text, code page 437 text, terminated (if less than 13 bytes) with LF and padded with SP. |
Currently defined descriptor types are:
0A 20 20.0A.| Bytes | Description |
|---|---|
| 0–4 | Standard header, byte 3 = 0xFD. |
| 5 | Minimum vertical field rate (1–255 Hz) |
| 6 | Maximum vertical field rate (1–255 Hz) |
| 7 | Minimum horizontal line rate (1–255 kHz) |
| 8 | Maximum horizontal line rate (1–255 kHz) |
| 9 | Maximum pixel clock rate, rounded up to 10 MHz multiple (10–2550 MHz) |
| 10 | Extended timing information type:00: No information, padded with 0A 20 20 20 20 20 20.02: Secondary GTF supported, parameters as follows. |
| 11 | Reserved, must be 0. |
| 12 | Start frequency for secondary curve, divided by 2 kHz (0–510 kHz) |
| 13 | GTF C value, multiplied by 2 (0–127.5) |
| 14–15 | GTF M value (0–65535, little-endian) |
| 16 | GTF K value (0–255) |
| 17 | GTF J value, multiplied by 2 (0–127.5) |
| Bytes | Description | |
|---|---|---|
| 0–4 | Standard header, byte 3 = 0xFB. | |
| 5 | White point index number (1–255) Usually 1; 0 indicates descriptor not used. | |
| 6 | White point CIE xy coordinates least-significant bits (like EDID byte 26) | |
| Bits 7–4 | Unused, must be 0. | |
| Bits 3–2 | White point x value least-significant 2 bits | |
| Bits 1–0 | White point y value least-significant 2 bits | |
| 7 | White point x value most significant 8 bits (like EDID byte 27) | |
| 8 | White point y value most significant 8 bits (like EDID byte 28) | |
| 9 | Gamma value, minus 1, time 100 (1.0–3.54, like EDID byte 23) | |
| 10–14 | Second descriptor, like above. Index number usually 2. | |
| 15–17 | Unused, padded with 0A 20 20. |
|
The CEA EDID Timing Extension was first introduced in EIA/CEA-861, and has since been updated several times, most notably with the -861B revision (which was version 3 of the extension, adding Short Video Descriptors and advanced audio capability/configuration information), -861D (which contains updates to the audio segments), and -861E which is the most recent.
Version 1 (as defined in -861) allowed the specification of video timings only through the use of 18-byte Detailed Timing Descriptors (as detailed in EDID 1.3 data format above). In all cases, the "preferred" timing should be the first DTD listed in a CEA EDID Timing Extension.
Version 2 (as defined in -861A) added the capability to designate a number of DTDs as "native" and also included some "basic discovery" functionality for whether the display device contains support for "basic audio", YCbCr pixel formats, and underscan.
Per Version 3 (from the -861B spec), there are two different ways to specify the timings of available DTV formats: via the use of 18-byte Detailed Timing Descriptors as in Version 1 & 2, and via the use of the Short Video Descriptor (see below). HDMI 1.0 -1.3c uses this version.
Included in Version 3 are four new optional types of data blocks: Video Data Blocks (containing the aforementioned Short Video Descriptors), Audio Data Blocks (containing Short Audio Descriptors), Speaker Allocation Data Blocks (containing information about the speaker configuration of the display device), and Vendor Specific Data Blocks (which can contain information specific to a given vendor's use).
Byte sequence
00: Extension tag (which kind of extension block this is); 02h for CEA EDID
01: Revision number (Version number); 03h for Version 3
02: Byte number "d" within this block where the 18-byte DTDs begin. If no non-DTD data is present
in this extension block, the value should be set to 04h (the byte after next). If set to 00h,
there are no DTDs present in this block and no non-DTD data.
03: Number of DTDs present, other Version 2+ information
bit 7: 1 if display supports underscan, 0 if not
bit 6: 1 if display supports basic audio, 0 if not
bit 5: 1 if display supports YCbCr 4:4:4, 0 if not
bit 4: 1 if display supports YCbCr 4:2:2, 0 if not
bit 3..0: total number of native formats in the DTDs included in this block
04: Start of Data Block Collection. If byte 02 is set to 04h, this is where the DTD collection
begins. If byte 02 is set to another value, byte 04 is where the Data Block Collection begins,
and the DTD collection follows immediately thereafter.
The Data Block Collection contains one or more data blocks detailing video, audio, and speaker
placement information about the display. The blocks can be placed in any order, and the initial
byte of each block defines both its type and its length:
bit 7..5: Block Type Tag (1 is audio, 2 is video, 3 is vendor specific, 4 is speaker
allocation, all other values Reserved)
bit 4..0: Total number of bytes in this block following this byte
Once one data block has ended, the next byte is assumed to be the beginning of the next data
block. This is the case until the byte (designated in Byte 02, above) where the DTDs are known
to begin.
Any Audio Data Block contains one or more 3-byte Short Audio Descriptors (SADs). Each SAD
details audio format, channel number, and bitrate/resolution capabilities of the display as
follows:
SAD Byte 1 (format and number of channels):
bit 7: Reserved (0)
bit 6..3: Audio format code
1 = Linear Pulse Code Modulation (LPCM)
2 = AC-3
3 = MPEG1 (Layers 1 and 2)
4 = MP3
5 = MPEG2
6 = AAC
7 = DTS
8 = ATRAC
0, 15: Reserved
9 = One-bit audio aka SACD
10 = DD+
11 = DTS-HD
12 = MLP/Dolby TrueHD
13 = DST Audio
14 = Microsoft WMA Pro
bit 2..0: number of channels minus 1 (i.e. 000 = 1 channel; 001 = 2 channels; 111 =
8 channels)
SAD Byte 2 (sampling frequencies supported):
bit 7: Reserved (0)
bit 6: 192kHz
bit 5: 176kHz
bit 4: 96kHz
bit 3: 88kHz
bit 2: 48kHz
bit 1: 44kHz
bit 0: 32kHz
SAD Byte 3 (bitrate):
For LPCM, bits 7:3 are reserved and the remaining bits define bit depth
bit 2: 24 bit
bit 1: 20 bit
bit 0: 16 bit
For all other sound formats, bits 7..0 designate the maximum supported bitrate divided by
8 kbit/s.
Any Video Data Block will contain one or more 1-byte Short Video Descriptors (SVDs). They are
decoded as follows:
bit 7: 1 to designate that this should be considered a "native" resolution, 0 for non-native
bit 6..0: index value to a table of standard resolutions/timings from CEA/EIA-861E:
Code
Short Aspect
Name Ratio HxV @ F
1 DMT0659 4:3 640x480p @ 59.94/60Hz
2 480p 4:3 720x480p @ 59.94/60Hz
3 480pH 16:9 720x480p @ 59.94/60Hz
4 720p 16:9 1280x720p @ 59.94/60Hz
5 1080i 16:9 1920x1080i @ 59.94/60Hz
6 480i 4:3 720(1440)x480i @ 59.94/60Hz
7 480iH 16:9 720(1440)x480i @ 59.94/60Hz
8 240p 4:3 720(1440)x240p @ 59.94/60Hz
9 240pH 16:9 720(1440)x240p @ 59.94/60Hz
10 480i4x 4:3 (2880)x480i @ 59.94/60Hz
11 480i4xH 16:9 (2880)x480i @ 59.94/60Hz
12 240p4x 4:3 (2880)x240p @ 59.94/60Hz
13 240p4xH 16:9 (2880)x240p @ 59.94/60Hz
14 480p2x 4:3 1440x480p @ 59.94/60Hz
15 480p2xH 16:9 1440x480p @ 59.94/60Hz
16 1080p 16:9 1920x1080p @ 59.94/60Hz
17 576p 4:3 720x576p @ 50Hz
18 576pH 16:9 720x576p @ 50Hz
19 720p50 16:9 1280x720p @ 50Hz
20 1080i25 16:9 1920x1080i @ 50Hz*
21 576i 4:3 720(1440)x576i @ 50Hz
22 576iH 16:9 720(1440)x576i @ 50Hz
23 288p 4:3 720(1440)x288p @ 50Hz
24 288pH 16:9 720(1440)x288p @ 50Hz
25 576i4x 4:3 (2880)x576i @ 50Hz
26 576i4xH 16:9 (2880)x576i @ 50Hz
27 288p4x 4:3 (2880)x288p @ 50Hz
28 288p4xH 16:9 (2880)x288p @ 50Hz
29 576p2x 4:3 1440x576p @ 50Hz
30 576p2xH 16:9 1440x576p @ 50Hz
31 1080p50 16:9 1920x1080p @ 50Hz
32 1080p24 16:9 1920x1080p @ 23.98/24Hz
33 1080p25 16:9 1920x1080p @ 25Hz
34 1080p30 16:9 1920x1080p @ 29.97/30Hz
35 480p4x 4:3 (2880)x480p @ 59.94/60Hz
36 480p4xH 16:9 (2880)x480p @ 59.94/60Hz
37 576p4x 4:3 (2880)x576p @ 50Hz
38 576p4xH 16:9 (2880)x576p @ 50Hz
39 1080i25 16:9 1920x1080i(1250 Total) @ 50Hz*
40 1080i50 16:9 1920x1080i @ 100Hz
41 720p100 16:9 1280x720p @ 100Hz
42 576p100 4:3 720x576p @ 100Hz
43 576p100H 16:9 720x576p @ 100Hz
44 576i50 4:3 720(1440)x576i @ 100Hz
45 576i50H 16:9 720(1440)x576i @ 100Hz
46 1080i60 16:9 1920x1080i @ 119.88/120Hz
47 720p120 16:9 1280x720p @ 119.88/120Hz
48 480p119 4:3 720x480p @ 119.88/120Hz
49 480p119H 16:9 720x480p @ 119.88/120Hz
50 480i59 4:3 720(1440)x480i @ 119.88/120Hz
51 480i59H 16:9 720(1440)x480i @ 119.88/120Hz
52 576p200 4:3 720x576p @ 200Hz
53 576p200H 16:9 720x576p @ 200Hz
54 576i100 4:3 720(1440)x576i @ 200Hz
55 576i100H 16:9 720(1440)x576i @ 200Hz
56 480p239 4:3 720x480p @ 239.76/240Hz
57 480p239H 16:9 720x480p @ 239.76/240Hz
58 480i119 4:3 720(1440)x480i @ 239.76/240Hz
59 480i119H 16:9 720(1440)x480i @ 239.76/240Hz
60 720p24 16:9 1280x720p @ 23.98/24Hz
61 720p25 16:9 1280x720p @ 25Hz
62 720p30 16:9 1280x720p @ 29.97/30Hz
63 1080p120 16:9 1920x1080p @ 119.88/120Hz
0, 64 - 127 Reserved
*Short video descriptors 20 & 39 are both 1920x1080i@50 16:9 but differ in the amount of vertical
total lines which are 1125 and 1250, respectively.
Notes: Parentheses indicate instances where pixels are repeated to meet the minimum speed
requirements of the interface. For example, in the 720X240p case, the pixels on each line
are double-clocked. In the (2880)X480i case, the number of pixels on each line, and thus
the number of times that they are repeated, is variable, and is sent to the DTV monitor by
the source device.
Increased Hactive expressions include “2x” and “4x” indicate two and four times the reference
resolution, respectively.
The CEA/EIA-861/A standard included only numbers 1-7 and numbers 17-22 above(but not as short
video descriptors which were introduced in CEA/EIA-861B) and are considered primary video format
timings.
The CEA/EIA-861B standard included the first 34 short video descriptors above.
The CEA/EIA-861D standard included the first 59 short video descriptors above.
HDMI 1.0 to HDMI 1.2a uses the CEA-861-B video standard, HDMI 1.3 to HDMI 1.3c uses the
CEA-861-D video standard, and HDMI 1.4 uses the CEA/EIA-861E video standard.
A Vendor Specific Data Block (if any) contains as its first three bytes the vendor's IEEE
24-bit registration number, LSB first. For HDMI, it is always 00-0C-03 for HDMI Licensing, LLC.
It is followed by a two byte source physical address, LSB first. The source physical address
provides the CEC physical address for upstream CEC devices.
The remainder of the Vendor Specific Data Block is the "data payload",which can be anything the
vendor considers worthy of inclusion in this EDID extension block. HDMI 1.3a specifies some
requirements for the data payload. See that spec for detailed info on these bytes:
VSD Byte 1-3 IEEE Registration Identifier (LSB First)
VSD Byte 4-5 Components of Source Physical Address (See section 8.7 of HDMI 1.3a)
VSD Byte 6 (bits are set if sink supports...):
bit 7: Supports_AI (...a function that needs info from ACP or ISRC packets)
bit 6: DC_48bit (...16-bit-per-channel deep color)
bit 5: DC_36bit (...12-bit-per-channel deep color)
bit 4: DC_30bit (...10-bit-per-channel deep color)
bit 3: DC_Y444 (...4:4:4 in deep color modes)
bit 2: Reserved (0)
bit 1: Reserved (0)
bit 0: DVI_Dual (...DVI Dual Link Operation)
VSD Byte 7 If non-zero (Max_TMDS_Frequency / 5mhz)
VSD Byte 8 (latency fields indicators):
bit 7: latency_fields (set if latency fields are present)
bit 6: i_latency_fields (set if interlaced latency fields are present; if set
four latency fields will be present, 0 if bit 7 is 0)
bits 5-0: Reserved (0)
VSD Byte 9 Video Latency (if indicated, value=1+ms/2 with a max of 251 meaning 500ms)
VSD Byte 10 Audio Latency (video delay for progressive sources, same units as above)
VSD Byte 11 Interlaced Video Latency (if indicated, same units as above)
VSD Byte 12 Interlaced Audio Latency (video delay for interlaced sources, same units as above)
Additional bytes may be present, but the HDMI spec says they shall be zero.
If a Speaker Allocation Data Block is present, it will consist of three bytes. The second and
third are Reserved (all 0), but the first contains information about which speakers are present in
the display device:
bit 7: Reserved (0)
bit 6: Rear Left Center / Rear Right Center present for 1, absent for 0
bit 5: Front Left Center / Front Right Center present for 1, absent for 0
bit 4: Rear Center present for 1, absent for 0
bit 3: Rear Left / Rear Right present for 1, absent for 0
bit 2: Front Center present for 1, absent for 0
bit 1: LFE present for 1, absent for 0
bit 0: Front Left / Front Right present for 1, absent for 0
Note that for speakers with right and left polarity, it is assumed that both
left and right are present.
"d": byte (designated in byte 02) where DTDs begin. 18-byte DTD strings continue for an unspecified
length (modulo 18) until a "00 00" is as the first bytes of a prospective DTD. At this point,
the DTDs are known to be complete, and the start address of the "00 00" can be considered to be "XX"
(see below)
"XX"-126: Post-DTD padding. Should be populated with 00h
127: Checksum - This byte should be programmed such that the sum of all 128 bytes equals 00h.